Electrical distance-based remapping in a memory device
AssigneeMicron Technology, Inc.
InventorHari Giduturi
Life of this patent
Estimating the term…
Abstract
Memory device systems and methods for using methods include multiple access lines arranged in a grid. Multiple memory cells are located at intersections of the access lines in the grid. Multiple drivers are included with each configured to transmit a corresponding signal to respective memory cells of the multiple memory cells. Remapping circuitry is configured to remap a near memory cell of the multiple memory cells to a far memory cell of the multiple memory cells. The near memory cell is relatively nearer to a respective driver of the multiple drivers than the far memory cell is to a respective driver of the multiple drivers.
Claims20
A device, comprising:
- a plurality of access lines arranged in a grid;
- a plurality of memory cells located at intersections of the access lines in the grid;
- a plurality of drivers, each configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells;
- and
- remapping circuitry configured to remap a near memory cell of the plurality of memory cells to a far memory cell of the plurality of memory cells, wherein the near memory cell is relatively nearer to a respective driver of the plurality of drivers than the far memory cell is to a respective driver of the plurality of drivers.
A method, comprising:
- receiving, at remapping circuitry, an indication of a memory cell of a plurality of memory cells of a memory device, wherein the plurality of memory cells are distributed in a memory array at a plurality of intersections of wordlines and bitlines of the memory device, wherein the indication provides that the memory cell is to-be-accessed and is located at a particular intersection of the wordlines and the bitlines;
- determining, using the remapping circuitry, that the memory cell is susceptible to a rush current spike above a rush threshold value;
- and
- remapping, using the remapping circuitry, the memory cell to another memory cell based at least in part on the determination that the memory cell is susceptible to the rush current spike being above the rush threshold value when the memory cell is turned on.
A memory device, comprising:
- a plurality of bitlines arranged in parallel to each other in a plurality of regions of the memory device;
- a plurality of wordlines arranged parallel to each other and perpendicular to the plurality of bitlines in the plurality of regions of the memory device;
- a plurality of memory cells located at intersections of the plurality of bitlines and the plurality of wordlines in the plurality of regions;
- a plurality of local drivers configured to drive the plurality of memory cells via the plurality of wordlines and the plurality of bitlines;
- and
- a mapping circuitry configured to
- receive an address of a memory cell of the plurality of memory cells;
- determine that the memory cell is within a threshold distance of a respective local driver of the plurality of local drivers;
- and
- remap the address to an address of another memory cell of the plurality of memory cells based at least in part on the determination that the memory cell is within the threshold distance of the respective local driver.
Dependencies are inferred from the claim text.