Non-destructive mode cache programming in nand flash memory devices

A method of cache programming of a NAND flash memory in a triple-level-cell (TLC) mode, wherein the NAND flash memory comprises a first set of data latches in a plurality of page buffers and a plurality of memory cells in a memory page, the method comprising:

• verifying a first group of logic states in the plurality of memory cells;
• discarding a lower page of a first programming data from the first set of data latches after the first group of logic states are programmed and verified, wherein
• each of the plurality of memory cells comprises 8 logic states, the 8 logic states comprising an erased state and ith logic states, wherein
• 1=1 to 7;
• and
• threshold voltages of the 8 logic states are in an ascending order;
• each of the plurality of memory cells is coupled to at least one of the plurality of page buffers;
• and
• the plurality of page buffers comprises the first set of data latches, a second set of data latches and a third set of data latches, configured to store the lower page, a middle page and an upper page of programming data, respectively;
• and
• uploading a lower page of second programming data to a set of cache latches in the plurality of page buffers.