Systems and Methods for Improved Data Access Speed
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorSanjeev Kumar Jain
Life of this patent
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Abstract
Systems and methods are provided for a memory device. A memory device includes a memory array, a column selection circuit coupled to the memory array, where the column selection circuit is configured to generate a column selection signal, and a sense amplifier configured to receive data signals from the memory array. An enable signal generating circuit is configured to generate a first enable signal and a second enable signal. The column selection circuit generates the column selection signal based on the first enable signal, and the sense amplifier is configured to receive a data signal from the memory array in response to the second enable signal.
Claims20
A memory device, comprising:
- a memory array;
- a column selection circuit coupled to the memory array, wherein the column selection circuit is configured to generate a column selection signal;
- a sense amplifier configured to receive data signals from the memory array;
- and
- an enable signal generating circuit configured to generate a first enable signal and a second enable signal;
- wherein the column selection circuit generates the column selection signal based on the first enable signal, and wherein the sense amplifier is configured to receive a data signal from the memory array in response to the second enable signal.
A method of operating a memory device, comprising:
- generating a first enable signal and a second enable signal;
- providing the first enable signal to a column selection circuit and the second enable signal to a sense amplifier circuit;
- using the column selection circuit to generate a column selection signal to a memory device based upon the first enable signal;
- receiving a data signal from the memory array at the sense amplifier in response to the second enable signal.
An enable signal generator, comprising:
- an input configured to receive an input enable signal;
- logic for generating a first enable signal based on the input enable signal, said first enable signal being routed to a memory array column selection circuit;
- logic for generating a second enable signal based on the input enable signal, said second enable signal being routed to a sense amplifier.
Dependencies are inferred from the claim text.