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US 2022/0068371 A1Published application
Pseudo-triple-port sram
AssigneeQUALCOMM Incorporated
InventorsArun Babu PALLERLA, Changho JUNG, Sung SON
Life of this patent
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Abstract
A pseudo-triple-port memory is provided that includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port including a first word line coupled to a first bit line through a first access transistor, a second read port including a second word line coupled to a second bit line through a second access transistor, and a write port including both the word lines, both the bit lines, and the pair of access transistors.
Claims27
A memory, comprising:
- a first bit line;
- a second bit line;
- a first bitcell including:
- a first pair of cross-coupled inverters having an output node for a first bit and a complement output node for a complement of the first bit, a first access transistor coupled between the output node and the first bit line, and a second access transistor coupled between the complement output node and the second bit line;
- a first word line coupled to a gate of the first access transistor;
- a second word line coupled to a gate of the second access transistor;
- a first multiplexer configured to select between a first read port address and a write address to provide a first address;
- a second multiplexer configured to select between a second read port address and a write address to provide a second address;
- a word line decoder configured to assert the first word line responsive to the first address and a first read port clock signal and to assert the second word line responsive to the second address and a second read port clock signal;
- and
- a word line controller configured to assert the first read port clock signal to perform a single-ended read of the first bit through the first bit line during a first portion of a first cycle of a memory clock signal and to assert both the first read port clock signal and the second read port clock signal during a second portion of the first cycle of the memory clock signal to perform a differential write of a second bit to the first bitcell.
8 more elements
A memory, comprising:
- a first column including a plurality of first bitcells;
- a first bit line for the first column;
- a second bit line for the first column;
- a plurality of word line pairs corresponding to the plurality of first bitcells, each first bitcell having a first read port coupled to the first bit line through a first access transistor configured to be controlled by a first word line in the corresponding pair of word lines, each first bitcell having a second read port coupled to the second bit line through a second access transistor configured to be controlled by a second word line in the corresponding pair of word lines and having a write port coupled to the first bit line and to the second bit line;
- and
- a word line controller configured to assert a first read port clock signal to trigger an assertion of the first word line in a first one of the word line pairs to perform a single-ended read of a first one of the first bitcells through the first bit line during a first portion of a cycle of a memory clock signal and to assert both the first read port clock signal and a second read port clock signal to trigger an assertion of the first word line and the second word line in the first one of the word line pairs during a second portion of the cycle of the memory clock signal to perform a differential write to the first one of the first bitcells.
3 more elements
A method for a pseudo-triple-port memory, comprising:
- selecting between a first read port address and a write address to provide a first address during a first portion of a first memory clock cycle;
- performing a single-ended read through a first bit line to a first bitcell responsive to an asserted first read port clock signal and the first address by asserting a first word line in a first pair of word lines for the first bitcell during the first portion of the first memory clock cycle;
- selecting between the first read port address and the write address to provide a second address, and
- asserting both the first word line and a second word line in the first pair of word lines responsive to the asserted first read port clock signal, an asserted second read port clock signal, and the second address to write to the first bitcell through the first bit line and through a second bit line during a second portion of the first memory clock cycle.
1 more element
Dependencies are inferred from the claim text.