Sram with advanced burst mode address comparator
AssigneeQUALCOMM Incorporated
InventorsChangho JUNG, Arun Babu PALLERLA, Percy DADABHOY
Life of this patent
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Abstract
A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A burst mode address comparator compares a current row address to a preceding row address from a preceding read operation to determine whether a read operation is a normal read operation or a burst mode read operation. The burst mode address comparator invokes the burst mode despite the presence of an intervening write operation to a row address not equal to the preceding row address.
Claims22
A burst mode address comparator for a memory, comprising:
- an address memory configured to store a first row address for a first read operation;
- a latch configured to set a latch output signal responsive to a second row address for a write operation following the first read operation being equal to the first row address;
- a first plurality of logic gates configured to assert a bit comparison word responsive to a current row address for the memory being equal to the first row address;
- a first transistor configured to switch off during each write operation and to switch on during each read operation;
- a second transistor having a first terminal coupled to a burst mode node for a burst mode signal and having a second terminal coupled to ground through the first transistor;
- and
- a second plurality of logic gates configured to switch on the second transistor to ground the burst mode node responsive to an assertion of the bit comparison word while the latch output signal is asserted and to not switch on the second transistor responsive to an assertion of the bit comparison word while the latch output signal is reset.
A burst mode method for a memory, comprising:
- pre-charging a pair of sense nodes for a sense amplifier during a first read operation to a first row in the memory:
- latching a first bit signal in the sense amplifier after the pre-charging;
- in a write operation after the first read operation, writing to a second row in the memory;
- and
- in a second read operation to the first row following the write operation, transferring the first bit signal latched in the sense amplifier to a data output latch without pre-charging the pair of sense nodes during the second read operation.
A memory, comprising:
- a word line;
- a plurality of columns, each column in the plurality of columns including a bitcell at an intersection of the column with the word line, a pair of bit lines, and a sense amplifier coupled to the pair of bit lines through a pair of sense nodes;
- a burst mode blocking latch configured to set a latch output signal responsive to a write operation to a first row address after an initial read operation to the first row address;
- a burst mode address comparator configured to determine for a series of subsequent read operations following the initial read operation whether each subsequent read operation is a burst mode read operation or a random read operation responsive to a row address for each subsequent read cycle and responsive to the latch output signal;
- and
- a sense node pre-charge circuit configured to pre-charge each column's pair of sense nodes in each random read operation and to not pre-charge each column's pair of sense nodes in each burst mode read operation.
Dependencies are inferred from the claim text.