Pseudo-triple-port sram bitcell architecture

A method, comprising:

• forming a bitcell arranged on a semiconductor substrate, the bitcell having a bitcell width and a bitcell height and including a first access transistor and a second access transistor;
• patterning a first metal layer adjacent the semiconductor substrate to form a pair of local bit lines arranged within the bitcell width, the pair of local bit lines including a local bit line coupled to a terminal of the first access transistor and including a complement local bit line coupled to a terminal of the second access transistor;
• and
• patterning a third metal layer adjacent to a second metal layer that is adjacent to the first metal layer to form a pair of word lines arranged within the bitcell height, the pair of word lines including a first read port word line coupled to a gate of the first access transistor and including a second read port word line coupled to a gate of the second access transistor.

A memory, comprising:

• a semiconductor substrate;
• a bitcell arranged on the semiconductor substrate, the bitcell having a bitcell width and a bitcell height and including a first access transistor and a second access transistor;
• a first metal layer adjacent the semiconductor substrate, the first metal layer being patterned to form a pair of local bit lines arranged within the bitcell width;
• the pair of local bit lines including a local bit line coupled to a terminal of the first access transistor and including a complement local bit line coupled to a terminal of the second access transistor;
• a second metal layer adjacent the first metal layer;
• and
• a third metal layer adjacent the second metal layer, the third metal layer being patterned to form a first pair of global bit lines for the bitcell.

A method, comprising:

• forming a bitcell arranged on a semiconductor substrate, the bitcell having a bitcell width and a bitcell height and including a first access transistor and a second access transistor;
• patterning a first metal layer adjacent the semiconductor substrate to form a pair of local bit lines arranged within the bitcell width, the pair of local bit lines including a local bit line coupled to a terminal of the first access transistor and including a complement local bit line coupled to a terminal of the second access transistor;
• and
• patterning a third metal layer adjacent to a second metal layer that is adjacent to the first metal layer to form a first pair of global bit lines for the bitcell.