Memory circuit, electronic device having the memory circuit, and method of operating memory circuit

An electronic device having a memory device comprising a memory circuit, wherein the memory circuit comprising:

• a voltage equalizing circuit configured to equalize and pre-charge a first data line and a second data line to a reference voltage upon receive a data line equalizing bar signal;
• a sense amplifier circuit electrically connected to the voltage equalizing circuit and configured to sense a binary data based on a relative voltage between the first data line and the second data line and comprising a comparator latch circuit for sensing the binary data and a data-in transistor for controlling the comparator latch circuit;
• a read-out latch circuit electrically connected to the sense amplifier circuit and configured to receive the binary data which is to be transmitted to an external controller;
• and
• a write circuit electrically and directly connected to the voltage equalizing circuit and configured to receive a first signal of the first data line and a second signal of the second data line so as to write the first signal to a first bit line and the second signal to a second bit line,
• wherein the data-in transistor is electrically connected to the comparator latch circuit and is configured to receive a data-in clock signal which turns on the data-in transistor which activates the comparator latch circuit so as to latch the first signal of the first data line and the second signal of the second data line,
• wherein sense amplifier circuit further comprising:
• a first data input transistor configured to receive a data-in clock bar signal which turns on the first data input transistor to receive a data input signal for the first data line;
• and
• a second data input transistor configured to receive the data-in clock bar signal which turns on the second data input transistor to receive a data in bar signal for the second data line during a write operation.

A method of operating a memory circuit comprising:

• receiving, by a voltage equalizing circuit, a data line equalizing bar signal to equalize and pre-charge a first data line and a second data line;
• sensing, by a sense amplifier circuit having a comparator latch circuit which is electrically connected to the voltage equalizing circuit, a binary data based on a relative voltage between the reference voltage on one of either the first data line or the second data line and a low voltage on the other one of either the first data line or the second data line;
• receiving, by a read-out latch circuit electrically connected to the sense amplifier circuit, the binary data which is to be transmitted to an external controller;
• receiving, by a write circuit electrically and directly connected to the voltage equalizing circuit, a first signal of the first data line and a second signal of the second data line so as to write the first signal to a first bit line and the second signal to a second bit line;
• receiving a data-in clock signal, by using a data-in transistor electrically connected to the comparator latch circuit, to turn on the data-in transistor which activates the comparator latch circuit so as to latch the first signal of the first data line and the second signal of the second data line;
• receiving, by a first data input transistor, a data-in clock bar signal which turns on the first data input transistor to receive a data input signal for the first data line;
• and
• receiving, by a second data input transistor, a data-in clock bar signal which turns on the second data input transistor to receive a data in bar signal for the second data line during a write operation, wherein the data-in clock signal turns off the data-in transistor and the data-in clock bar signal turns off the first data input transistor and the second data input transistor during a read operation.