Semiconductor device and method for operating the same

A semiconductor device, comp sing:

• a first pull-up transistor and a first pull-down transistor coupled to a through line by a first common node and receiving a driving control signal transferred from a first global line or a second global line according to an output control signal to drive the first common node;
• a second pull-up transistor and a second pull-down transistor coupled to the first global line by a second common node and receiving a signal transferred through the through line according to a first input control signal to drive the second common node;
• a third pull-up transistor and a third pull-down transistor coupled to the second global line through a third common node and receiving a signal transferred through the through line according to a second input control signal to drive the third common node;
• and
• a deterioration acceleration circuit for applying stress to the first to third pull-up transistors according to a test signal.

A method for operating a semiconductor device, the method comprising:

• driving a first common node coupling a first pull up transistor and a first pull down transistor and also coupled to a through line, receiving a signal transferred through the through line, and driving a second common node coupling a second pull up transistor and a second pull down transistor and also coupled to a first global line, and receiving a signal transferred through the through line and driving a third common node coupling a third pull up transistor and a second pull down transistor and also coupled to a second global line;
• performing a deterioration acceleration operation for applying a stress to the first to third pull-up transistors during a test operation;
• and
• driving the first to third common nodes at a ground voltage level during a normal operation.

A semiconductor device, comprising:

• a first driving circuit including a first transistor and a second transistor coupled in series between a first voltage terminal and a second voltage terminal, and a first common node coupled between the first transistor and the second transistor and coupled to a scheduled line, the first driving circuit transferring data transferred from a first pad group to the scheduled line according to a first driving control signal;
• a second driving circuit including a third transistor and a fourth transistor coupled in series between the first voltage terminal and the second voltage terminal, and a second common node coupled between the third transistor and the fourth transistor and coupled to a scheduled line, the second driving circuit transferring data transferred from a second pad group to the scheduled line according to a second driving control signal;
• and
• a deterioration acceleration circuit for applying a stress to the third transistor according to a test signal.