Power network for providing power supply to memory device
AssigneeArm Limited
InventorsAndy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
Life of this patent
Estimating the term…
Abstract
Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.
Claims20
A device, comprising:
- memory circuitry having a bitcell array;
- a frontside power network coupled to the bitcell array;
- a backside power network that provides power to the bitcell array;
- and
- transition vias that couple the backside power network to the frontside power network,
- wherein:
- the backside power network provides power to the bitcell array by way of the transition vias being coupled to the frontside power network, the transition vias couple the backside power network to control logic, and the backside power network provides power to the control logic by way of the transition vias.
A device, comprising:
- memory circuitry having control logic;
- a backside power network that provides power to the control logic;
- and
- transition vias that couple the backside power network to the control logic,
- wherein the backside power network provides power directly to the control logic by way of the transition vias.
A method, comprising:
- providing memory circuitry with a bitcell array and control logic;
- coupling a frontside power network to the bitcell array;
- coupling a backside power network to the frontside power network with transition vias;
- coupling the backside power network to the control logic with the transition vias;
- and
- providing power from the backside power network to the bitcell array and the control logic of the memory circuitry.
Dependencies are inferred from the claim text.