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US 2022/0068345 A1Published application
Compensating for kickback noise
AssigneeMicron Technology, Inc.
InventorsWei Lu Chu, Dong Pan
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for compensating for kickback noise are described. A regulator may include an input circuit, a bias circuit, and an enable circuit. The regulator may be configured so that the enable circuit is positioned between the input circuit and the bias circuit. A balance resistor may be included in a path between an input of the regulator and a gate of a bias transistor included in the bias transistor. A size of the balance resistor may be based on an amount of charge drawn by the bias transistor during an activation event. Dimensions of the bias transistor may be modified based on an amount of charge drawn by the bias transistor during an activation event.
Claims34
An apparatus, comprising:
- a memory array comprising one or more components;
- and
- a regulator coupled with the memory array and configured to generate a signal for the memory array based at least in part on a reference signal, the regulator comprising:
- an input circuit configured to receive the reference signal at an input node;
- a biasing circuit coupled with the input node and configured to bias the regulator based at least in part on the reference signal;
- and
- an enable circuit coupled with the input circuit via a first node and the biasing circuit via a second node, the enable circuit configured to enable an operation of the regulator and configured to reduce noise at the input node that is based at least in part on the operation of the regulator being enabled.
4 more elements
An apparatus, comprising:
- a memory array comprising a plurality of memory sections;
- a plurality of regulators coupled with the plurality of memory sections, wherein a regulator of the plurality of regulators comprises:
- a first transistor coupled with an input node and configured to receive a reference signal;
- a second transistor coupled with the input node and configured to bias the regulator based at least in part on the reference signal;
- and
- a third transistor coupled with the first transistor via a first node and coupled with the second transistor via a second node, the third transistor configured to enable an operation of the regulator based at least in part on receiving an enable signal at a gate of the third transistor.
3 more elements
A method, comprising:
- powering a memory device comprising a memory array and a regulator having a first transistor for receiving a reference signal, a second transistor for biasing the regulator, and a third transistor for enabling an operation of the regulator, wherein a voltage of a first node that is coupled with the first transistor and the third transistor has a first level and a voltage of a second node that is coupled with the second transistor and the third transistor has a second level based at least in part on the memory device being powered and the third transistor being deactivated;
- receiving a command to activate a section of the memory array that is coupled with the regulator based at least in part on the memory device being powered;
- and
- activating the second transistor based at least in part on the command, wherein, based at least in part on activating the second transistor, the voltage of the first node and the voltage of the second node have a third level that is between the first level and the second level and the regulator generates a power signal for one or more sensing components in the section of the memory array.
1 more element
An apparatus, comprising:
- a memory array comprising one or more sensing components;
- a regulator coupled with the memory array and configured to generate a power signal for the one or more sensing components based at least in part on a reference signal associated with the one or more sensing components, the regulator comprising:
- a differential input circuit configured to receive the reference signal and an output of the regulator,
- a biasing circuit configured to bias the regulator in an operational state, and
- an enable circuit coupled with the differential input circuit and the biasing circuit and configured to couple the differential input circuit with the biasing circuit based at least in part on an enable signal for the regulator, wherein a first node of the regulator is coupled with the differential input circuit and the enable circuit, and a second node of the regulator is coupled with the biasing circuit and the enable circuit, wherein the enable circuit is electrically positioned between the differential input circuit and the biasing circuit;
- and
- a controller coupled with the regulator and configured to cause the apparatus to:
- power the regulator causing a voltage of the first node to have a first level and a voltage of the second node to have a second level;
- and
- activate the enable circuit based at least in part on the regulator being powered causing the voltage of the first node and the voltage of the second node to have a third level that is between the first level and the second level.
7 more elements
An apparatus, comprising:
- a memory device comprising:
- a memory array having a plurality of sections, and
- a regulator coupled with one or more sensing components included in a section of the plurality of sections and comprising a first transistor for receiving a reference signal, a second transistor for biasing the regulator, a third transistor for enabling an operation of the regulator, a first node that is coupled with the first transistor and the third transistor, and a second node that is coupled with the second transistor and the third transistor;
- and
- a controller coupled with the memory device and configured to cause the apparatus to:
- power the memory device, wherein a voltage of the first node transitions to a first level and a voltage of the second node transitions to a second level;
- receive a command to activate the section of the memory array that is coupled with the regulator;
- and
- activate the second transistor of the regulator based at least in part on the command, wherein the voltage of the first node and the voltage of the second node transitions to a third level that is between the first level and the second level and the regulator generates a power signal for the one or more sensing components based at least in part on activating the second transistor.
6 more elements
Dependencies are inferred from the claim text.