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US 2022/0068340 A1Published application
Non-volatile static random access memory
AssigneeGlobalFoundries U.S. Inc.
InventorsBipul C. Paul, Steven R. Soss
Life of this patent
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Abstract
Disclosed are embodiments of a non-volatile static random access memory (NV-SRAM) cell. The NV-SRAM cell includes a static random access memory (SRAM) circuit (e.g., a conventional high performance, high reliability SRAM circuit). However, in order to avoid volatility while still retaining the advantages associated with SRAM circuit operation, the NV-SRAM cell also includes a pair of NVM circuits. These NVM circuits capture data values stored on the data nodes of the SRAM circuit prior to power down and rewrite those data values back onto the data nodes of the SRAM circuit upon power up. Also disclosed are embodiments of a method of operating a selected NV-SRAM cell in a memory array.
Claims20
A memory cell comprising:
- a static random access memory circuit comprising a first data node and a second data node;
- a first non-volatile memory circuit electrically connected in series between the first data node and a first non-volatile memory bitline, wherein the first non-volatile memory circuit comprises:
- a first access transistor connected to the first data node;
- and a first two-terminal non-volatile memory device connected between the first access transistor and the first non-volatile memory bitline;
- and
- a second non-volatile memory circuit electrically connected in series between the second data node and a second non-volatile memory bitline, wherein the second non-volatile memory circuit comprises:
- a second access transistor connected to the second data node;
- and a second two-terminal non-volatile memory device connected between the second access transistor and the second non-volatile memory bitline.
5 more elements
A memory array comprising:
- memory cells arranged in columns and rows, wherein each memory cell comprises:
- a static random access memory circuit electrically connected to a first static random access memory bitline for a specific column containing the memory cell and to a second static random access memory bitline for the specific column, wherein the static random access memory circuit comprises a first data node and a second data node;
- a first non-volatile memory circuit electrically connected in series between the first data node and a first non-volatile memory bitline of the specific column, wherein the first non-volatile memory circuit comprises:
- a first access transistor connected to the first data node;
- and a first two-terminal non-volatile memory device connected between the first access transistor and the first non-volatile memory bitline for the specific column;
- and
- a second non-volatile memory circuit electrically connected in series between the second data node and a second non-volatile memory bitline for the specific column, wherein the second non-volatile memory circuit comprises:
- a second access transistor connected to the second data node;
- and a second two-terminal non-volatile memory device connected between the second access transistor and the second non-volatile memory bitline for the specific column,
- wherein each memory cell is configured to enable a first data value from the first data node and a second data value from the second data node to be copied into the first non-volatile memory circuit and the second non-volatile memory circuit, respectively, so as to retain the first data value and the second data value when the memory array is powered down, and
- wherein each memory cell is further configured to enable the first data value and the second data value to be rewritten from the first non-volatile memory circuit and the second non-volatile memory circuit back to the first data node and the second data node, respectively, upon powering up of the memory array.
8 more elements
A method comprising:
- selecting a memory cell in a memory array, wherein the memory array comprising memory cells arranged in columns and rows, and wherein each memory cell comprises:
- a static random access memory circuit electrically connected to a first static random access memory bitline for a specific column containing the memory cell and to a second static random access memory bitline for the specific column, wherein the static random access memory circuit comprises a first data node and a second data node;
- a first non-volatile memory circuit electrically connected in series between the first data node and a first non-volatile memory bitline for the specific column, wherein the first non-volatile memory circuit comprises:
- a first access transistor connected to the first data node and a first two-terminal non-volatile memory device connected between the first access transistor and the first non-volatile memory bitline for the specific column;
- and
- a second non-volatile memory circuit electrically connected in series between the second data node and a second non-volatile memory bitline for the specific column wherein the second non-volatile memory circuit comprises:
- a second access transistor connected to the second data node and a second two-terminal non-volatile memory device connected between the second access transistor and the second non-volatile memory bitline for the specific column;
- in the selected memory cell in the memory array, copying a first data value from the first data node and a second data value from the second data node into the first non-volatile memory circuit and the second non-volatile memory circuit, respectively;
- and
- in the selected memory cell, rewriting the first data value and the second data value from the first non-volatile memory circuit and the second non-volatile memory circuit back to the first data node and the second data node, respectively.
7 more elements
Dependencies are inferred from the claim text.