Race-track memory with improved domain wall motion control

A system, comprising:

• a racetrack memory layer including:
• a plurality of bit locations;
• and
• a plurality of domain wall traps, the plurality of bit locations being interleaved with the plurality of domain wall traps, each of the plurality of bit locations having a first domain wall speed, each of the plurality of domain wall traps having a second domain wall speed, the first domain wall speed being greater than the second domain wall speed, the first domain wall speed and the second domain wall speed being due to at least one of a Dzyaloshinskii-Moriya interaction (DMI) variation in the racetrack memory layer, a synthetic antiferromagnetic (SAF) effect variation in the racetrack memory layer, and a separation distance for the plurality of domain wall traps corresponding to an intrinsic travel distance, the separation distance being at least twenty nanometers and not more than one hundred nanometers;
• wherein for the first domain wall speed and the second domain wall speed being due to the DMI variation in the racetrack memory layer, each of the plurality of bit locations has a first DMI and each of the plurality of domain wall traps has a second DMI, the first DMI being greater than the 0.05, and the second DMI being greater than zero and not more than 0.05;
• wherein for the first domain wall speed and the second domain wall speed being due to the SAF effect variation, the system further includes a nonmagnetic coupling layer and a ferromagnetic layer, the nonmagnetic coupling layer being between the ferromagnetic layer and the racetrack memory layer, the ferromagnetic layer being synthetic antiferromagnetically coupled with the racetrack memory layer, at least the ferromagnetic layer being configured to provide the SAF effect variation in the racetrack memory layer;
• and
• a spin orbit torque (SOT) layer configured to carry a current for programming the racetrack memory layer.

A method for providing a magnetic device, comprising:

• providing a racetrack memory layer, the providing the racetrack memory layer including:
• providing a plurality of bit locations;
• and
• providing a plurality of domain wall traps, the plurality of bit locations being interleaved with the plurality of domain wall traps, each of the plurality of bit locations having a first domain wall speed, each of the plurality of domain wall traps having a second domain wall speed, the first domain wall speed being greater than the second domain wall speed;
• wherein the first domain wall speed and the second domain wall speed are due to at least one of a Dzyaloshinskii-Moriya interaction (DMI) variation in the racetrack memory layer, a synthetic antiferromagnetic (SAF) effect variation in the racetrack memory layer, and a separation distance for the plurality of domain wall traps corresponding to an intrinsic travel distance, the separation distance being at least twenty nanometers and not more than one hundred nanometers.