Memory

A memory, comprising:

• at least one memory chip, each of the at least one memory chip comprising at least one channel, wherein each channel comprises:
• a plurality of banks, each bank comprising a plurality of memory cells, wherein the plurality of banks are configured to perform read and write operations alternately;
• a command port for each of the at least one memory chip, configured to receive command signals at a preset edge of a command clock, wherein the command signals are configured to control the read and write operations of the plurality of banks;
• and
• a data port for each of the at least one memory chip, configured to receive data signals to be written into the banks or transmit data signals at a preset edge of a data clock;
• wherein the command port comprises a row address port and a column address port, the row address port is configured to receive a row address signal at a position of a target memory cell, the column address port is configured to receive a column address signal at a position of the target memory cell, and the target memory cell is selected from the plurality of memory cells.