Interface circuit, data transmission circuit, and memory

An interface circuit, comprising:

• a clock pad, configured to transmit a clock signal;
• M data pads, configured to transmit data signals;
• and
• M input buffer circuits in one-to-one correspondence with the data pads, each of the input buffer circuits being driven by the clock signal to receive a data signal transmitted by a data pad corresponding to the input buffer circuit,
• wherein the clock pad and the data pads are arranged in a first row, and the M data pads are arranged on two sides of the clock pad, half of the M data pads being arranged on each side, wherein the M input buffer circuits are arranged in a second row and form an axis perpendicular to the first row with the clock pads as reference, and the M input buffer circuits are arranged on two sides of the axis, half of the M input buffer circuits being arranged on each side, and wherein a distance between each of the input buffer circuits and the axis is smaller than a distance between a data pad corresponding to the input buffer circuit and the axis, M being an integer larger than or equal to 2.