Systems and methods for controlling power management operations in a memory device

A method for controlling a wake-up operation for a memory array that includes a plurality of memory cells, comprising:

• receiving a sleep signal indicating an initiation of the wake-up operation;
• generating, at first logic circuitry, a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, the first bit line pre-charge signal being generated in response to the sleep signal;
• pre-charging one or more bit line of the first memory cell in response to the first bit line pre-charge signal;
• generating, at a first latch circuit, a delayed sleep signal in response to the sleep signal and the first bit line pre-charge signal;
• generating, a second logic circuitry, a second bit line pre-charge signal for a second memory cell of the plurality of memory cells, the second logic circuitry being generated in response to the delayed sleep signal;
• and
• pre-charging one or more bit line of the second memory cell in response to the second bit line pre-charge signal.

A memory circuit comprising:

• a memory array that includes a plurality of memory cells;
• first logic circuitry configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, the first logic circuitry being configured to generate the first bit line pre-charge signal in response to a sleep signal;
• first switching circuitry configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal;
• a first latch circuit comprising a latch and a bit line delay tracking element,
• the latch being configured to generate a delayed sleep signal in response to the sleep signal and the first bit line pre-charge signal,
• the bit line delay tracking element being configured to delay operation of the latch by a time delay corresponding to an RC delay of the one or more bit line of the first memory cell;
• second logic circuitry configured to generate a second bit line pre-charge signal for a second memory cell of the plurality of memory cells, the second logic circuitry being configured to generate the second bit line pre-charge signal in response to the delayed sleep signal;
• and
• second switching circuitry configured to provide power to one or more bit line of the second memory cell in response to the second bit line pre-charge signal.