Page buffer circuit and memory device including the same

A memory device comprising:

• a memory cell array including a plurality of memory cell groups;
• a page buffer circuit including a plurality of page buffer groups respectively connected to the plurality of memory cell groups, wherein:
• each of the plurality of page buffer groups comprises a plurality of page buffer units arranged in a matrix form, and
• a plurality of first page buffer units in a first stage of each page buffer group are divided into a first group configured to perform a first sensing operation according to a first sensing signal and a second group configured to perform a second sensing operation according to a second sensing signal;
• a counting circuit configured to count a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and count a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation;
• and
• a control circuit configured to determine a development time period of the plurality of first page buffer units based on a comparison result of the first number of memory cells and the second number of memory cells.

A memory device comprising:

• a memory cell region including a plurality of memory cells and a first metal pad;
• and
• a peripheral circuit region including a second metal pad, the peripheral circuit region being perpendicularly connected to the memory cell region via the first metal pad and the second metal pad,
• wherein the peripheral circuit region comprises:
• a page buffer circuit comprising a first page buffer column and a second page buffer column, wherein:
• each of the first page buffer column and the second page buffer column comprises page buffer units arranged in a multi-stage structure,
• the first page buffer column includes a first page buffer unit in a first stage, the first page buffer unit configured to perform a first sensing operation in response to a first sensing signal, and
• the second page buffer column includes a second page buffer unit in the first stage, the second page buffer unit configured to perform a second sensing operation in response to a second sensing signal;
• and
• a counting circuit configured to count a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and count a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.