Techniques to manage execution of divergent shaders
AssigneeIntel Corporation
InventorsJohn G. GIERACH, Karthik VAIDYANATHAN, Thomas F. RAOUX
Life of this patent
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Abstract
Examples are described here that can be used to enable a main routine to request subroutines or other related code to be executed with other instantiations of the same subroutine or other related code for parallel execution. A sorting unit can be used to accumulate requests to execute instantiations of the subroutine. The sorting unit can request execution of a number of multiple instantiations of the subroutine corresponding to a number of lanes in a SIMD unit. A call stack can be used to share information to be accessed by a main routine after execution of the subroutine completes.
Claims20
An apparatus comprising:
- a memory device;
- execution logic including a plurality of single instruction multiple data (SIMD) execution units;
- a thread scheduler to dispatch at least one thread for execution by at least a portion of the execution logic;
- and
- sorting logic, wherein:
- the at least one thread comprises a first shader,
- execution of the first shader is to cause a request to perform a first subroutine, and
- in response to the request to perform a first subroutine, the sorting logic is to request the thread scheduler to dispatch execution of a combination of the first subroutine with zero or more other instances of the first subroutine based on a threshold number of requests to perform the first subroutine being met or exceeded.
At least one computer-readable medium comprising instructions stored thereon, that if executed by at least one processor, cause the at least one processor to:
- analyze a first shader to determine any branch with two divergent subroutines, the two divergent subroutines comprising a first subroutine and a second subroutine;
- form a function table comprising identification of the first shader, the first subroutine, and the second subroutine;
- execute the first shader;
- execute the first subroutine in parallel with zero or more instances of the first subroutine;
- and
- execute the second subroutine in parallel with zero or more instances of the second subroutine.
A system comprising:
- at least one memory;
- at least one processor;
- and
- at least one graphics processing unit communicatively coupled to the at least one memory and to the at least one processor, wherein:
- the at least one processor is to:
- request execution of a shader over data stored in the at least one memory using a portion of the at least one graphics processing unit, the shader comprising a first subroutine and
- dispatch execution of the first subroutine with zero or more other instances of the first subroutine using a portion of the at least one graphics processing unit in response to a threshold number of requests to perform the first subroutine being met or exceeded.
Dependencies are inferred from the claim text.