Sram architecture for convolutional neural network application

A method, by a memory controller, comprising:

• proceeding, starting with each of a plurality of reference bits in a first logic state such that a plurality of reference analog devices of a reference cell array is disabled, to search for an enabled subset of a plurality of first analog devices in a memory cell array, including:
• setting a first reference bit to a second logic state, thereby enabling a first subset of the plurality of reference analog devices;
• generating a first voltage at a first node coupled to the plurality of first analog devices and a second voltage at a second node coupled to the plurality of reference analog devices;
• comparing the first voltage and the second voltage;
• updating the first reference bit to one of the first logic state and the second logic state, based on the comparison;
• and
• storing the first reference bit,
• with the updated plurality of reference bits acting as an initial value for a next iteration, until the plurality of reference bits indicates the enabled subset of first analog devices.

A memory cell comprising:

• a cell core configured to store a weight bit;
• one or more analog device;
• and
• one or more switches configured to selectively couple, based on the weight bit and a digital input bit, the one or more analog devices to one of a sensing node or a reference node.