Cell overlap violation diagnostics with machine learning
AssigneeSynopsys, Inc.
InventorsLeslie K. HWANG, Srinivasa R. ARIKATI
Life of this patent
Estimating the term…
Abstract
A method for identifying design rule checking (DRC) violation types within an integrated circuit (IC) chip design includes receiving an IC chip design layout, and performing a DRC process on the IC chip design layout to identify DRC violations. Further, the method includes generating clustered heatmaps from heatmaps generated from the DRC violations. The method further includes identifying a first DRC violation type and a corresponding first cell pair within the IC chip design layout by analyzing the clustered heatmaps with a diagnostic model.
Claims20
A method for identifying design rule checking (DRC) violation types within an integrated circuit (IC) chip design, the method comprising:
- receiving an IC chip design layout;
- performing a DRC process on the IC chip design layout to identify DRC violations;
- generating, by one or more processors, clustered heatmaps from heatmaps generated from the DRC violations;
- and
- identifying, by the one or more processors, a first DRC violation type and a corresponding first cell pair within the IC chip design layout by analyzing the clustered heatmaps with a diagnostic model.
A system comprising:
- a memory storing instructions;
- and
- a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
- receive an integrated circuit (IC) design layout;
- perform a DRC process on the IC design layout to identify DRC violations;
- generate clustered heatmaps from heatmaps generated from the DRC violations;
- and
- identify a first DRC violation type and a corresponding first cell pair within the IC design layout by analyzing the clustered heatmaps with a diagnostic model.
A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
- receive an integrated circuit (IC) design layout;
- perform a design rule checking (DRC) process on the IC design layout to identify DRC violations;
- determine an error distribution across the IC design layout based on the DRC violations;
- and
- identify a first DRC violation type and a corresponding first cell pair within the IC design layout based on the error distribution across the IC design layout.
Dependencies are inferred from the claim text.