Structure and method of non-rectangular cell in semiconductor device

A layout method, executed by at least one processor, comprising:

• generating a design data comprising an electronic circuit;
• and
• generating a design layout by placing a first cell, wherein the first cell comprises:
• an active region extending in a first direction in a first layer;
• a first gate electrode extending in a second direction perpendicular to the first direction in a second layer over the first layer and crossing the active region;
• a first conductive line extending in a third direction in a third layer over the second layer;
• and
• a second conductive line extending in a fourth direction in a fourth layer over the third layer,
• wherein at least one of the third direction and the fourth direction is different from the first and second directions.

A semiconductor device comprising:

• a cell, comprising:
• a first source/drain region and a second source/drain region arranged in a first layer;
• a first gate electrode extending in a first direction in a second layer over the first layer, wherein the first and second source/drain regions are disposed on opposite sides of the first gate electrode;
• a first power rail extending in a second direction perpendicular to the first direction in a third layer over the second layer;
• a second power rail extending in the second direction on a side of the cell opposite to the first power rail;
• and
• a first conductive line extending in a third direction over the first layer, wherein the third direction is not parallel to the first direction and not parallel to the second direction.