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AssigneesSumitomo Electric Industries, Ltd., National University Corporation Hokkaido University
InventorsKenya NISHIGUCHI, Tamotsu HASHIZUME
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With respect to a method of simulating a capacitance-voltage (C-V) characteristic of a laminated structure that includes a semiconductor, an insulator provided on the semiconductor, and a metal provided on the insulator, and that includes multiple discrete interface states, at which electrons are trapped or emitted in response to a change of a voltage applied to the metal, at an interface between the semiconductor and the insulator, the method includes calculating a first capacitance in accordance with a first voltage applied to the metal, and calculating a second capacitance from a quantity of electrons emitted from a first interface state corresponding to the first voltage among the multiple discrete interface states. The calculating of the second capacitance includes changing the first voltage in stages and shifting the first interface state in stages.
A method of simulating a capacitance-voltage (C-V) characteristic of a laminated structure including a semiconductor, an insulator provided on the semiconductor, and a metal provided on the insulator, the method using a model of the C-V characteristic of the laminated structure that includes a plurality of discrete interface states, at which electrons are trapped or emitted in response to a change of a voltage applied to the metal, at an interface between the semiconductor and the insulator, the model of the C-V characteristic representing a third capacitance in response to the change of the voltage, the third capacitance including a first capacitance of a depletion layer formed at the interface, a second capacitance of the plurality of discrete interface states, and a capacitance of the insulator, the first capacitance and the second capacitance being connected in parallel, the capacitance of the insulator being connected in series with the first capacitance and the second capacitance connected in parallel, and the method comprising:
A non-transitory computer-readable recording medium having stored therein a program for causing a computer to perform a process of simulating a capacitance-voltage (C-V) characteristic of a laminated structure including a semiconductor, an insulator provided on the semiconductor, and a metal provided on the insulator, the process using a model of the C-V characteristic of the laminated structure that includes a plurality of discrete interface states, at which electrons are trapped or emitted in response to a change of a voltage applied to the metal, at an interface between the semiconductor and the insulator, the model of the C-V characteristic representing a third capacitance in response to the change of the voltage, the third capacitance including a first capacitance of a depletion layer formed at the interface, a second capacitance of the plurality of discrete interface states, and a capacitance of the insulator, the first capacitance and the second capacitance being connected in parallel, the capacitance of the insulator being connected in series with the first capacitance and the second capacitance connected in parallel, and the process comprising:
A device of simulating a capacitance-voltage (C-V) characteristic of a laminated structure including a semiconductor, an insulator provided on the semiconductor, and a metal provided on the insulator, by using a model of the C-V characteristic of the laminated structure that includes a plurality of discrete interface states, at which electrons are trapped or emitted in response to a change of a voltage applied to the metal, at an interface between the semiconductor and the insulator, the model of the C-V characteristic representing a third capacitance in response to the change of the voltage, the third capacitance including a first capacitance of a depletion layer foamed at the interface, a second capacitance of the plurality of discrete interface states, and a capacitance of the insulator, the first capacitance and the second capacitance being connected in parallel, the capacitance of the insulator being connected in series with the first capacitance and the second capacitance connected in parallel, and the device comprising:
Dependencies are inferred from the claim text.