A method for validating a hardware system

A computer-implemented method for automatically validating a hardware system by a model thereof, the model being a netlist at register transfer level, which netlist is bipartite having cells and links therebetween, the method comprising the following steps carried out by a computer:

• providing one or more reference structures, which structures are prone to error or manipulation, and determining, in the model, sub-structures, each of which sub-structures comprises a subset of the cells and links of the model and is structurally equivalent to one of said reference structures;
• extracting, from the model, input cones for each of the determined sub-structures, each input cone comprising control inputs to one of the cells of the sub-structure up to at least one of a nearest register output in the model and a nearest primary input to the model;
• creating a set of monopartite candidate graphs by mapping the cells and links of each sub-structure and of the respective input cones extracted for the sub-structure to nodes and edges of one of the monopartite candidate graphs of the set, wherein each node has a node type;
• creating, for each candidate graph, an n-dimensional match vector, each dimension of the match vector comprising a count of occurrences, in the candidate graph, of a different one of a number of n predetermined graphlets, wherein each graphlet has nodes and edges and each node has a node type;
• clustering, on the basis of similarity of the created match vectors, the candidate graphs in clusters;
• and
• selecting, from each of at least some of said clusters, one candidate graph and determining a functional behaviour of the sub-structure the selected candidate graph was mapped from for validating the hardware system.