US 2022/0067251 A1 · Formal Gated Clock Conversion for Field Programmable Gate Array (FPGA) Synthesis

Abstract

Some aspects of this disclosure are directed to implementing formal gated clock conversion for field programmable gate array (FPGA) synthesis. For example, some aspects of this disclosure relate to a method, including receiving network representation of a circuit design, determining a gated clock function corresponding to a target component of the network representation, and constructing an edge function based at least in part on the gated clock function. The method further includes performing a minimization of the edge function, and in response to a determination that the minimization of the edge function comprises a first term and a second term, providing a clock enable signal to the target component based on the first term, and providing a clock signal to the target component based on the second term.

Claims20

Dependent claims

A method comprising:

receiving network representation of a circuit design;
determining a gated clock function corresponding to a target component of the network representation;
constructing an edge function based at least in part on the gated clock function;
performing a minimization of the edge function;
and
in response to a determination that the minimization of the edge function comprises a first term and a second term, providing a clock enable signal to the target component based on the first term, and providing a clock signal to the target component based on the second term.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/411,695Filed 25 Aug 2021

Priority

25 Aug 2020

Published

3 Mar 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking
G06F 30/3312
Using simulation: timing analysis

Formal Gated Clock Conversion for Field Programmable Gate Array (FPGA) Synthesis

Life of this patent

Formal Gated Clock Conversion for Field Programmable Gate Array (FPGA) Synthesis

Life of this patent

Abstract

Claims20