Device and method for protecting a memory
AssigneeSecure-Ic SAS
InventorsMichel LE ROLLAND, Sylvain GUILLEY, Adrien FACON
Life of this patent
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AssigneeSecure-Ic SAS
InventorsMichel LE ROLLAND, Sylvain GUILLEY, Adrien FACON
Estimating the term…
Embodiments provide a memory device including a memory comprising at least one chip, each chip comprising one or more banks for storing a plurality of bits, each bank comprising a set of rows and columns, each row and column comprising a number of bits, the device further comprising a controller configured to generate access commands to the memory, an access command identifying an address corresponding to a given row of the memory and a command operation to be performed on the given row, wherein the device further comprises a protection device. The protection device is configured to transform an address, in response to the receipt of an access command identifying the address, into a transformed address. The protection device uses an address storage data structure, such as a histogram, to store the transformed address depending on a frequency of access associated with the address, the address storage data structure being reset in response to a memory protection operation (refresh for example) performed in the memory device. The protection device further comprises an access frequency manager configured to determine whether the access frequency associated with an address maintained in the address storage data structure is greater or equal to a threshold, and if so trigger a memory protection operation in the memory from within the memory.
A memory device comprising a memory comprising at least one chip, each chip comprising one or more banks for storing a plurality of bits, each bank comprising a set of rows and columns, each row and column comprising a number of bits, the device further comprising a controller configured to generate access commands to the memory, an access command identifying an address corresponding to a given row of the memory and a command operation to be performed on said given row, wherein the device further comprises a protection device, said protection device comprising:
A method for protecting a memory, said memory comprising at least one chip, each chip comprising one or more banks for storing a plurality of bits, each bank comprising a set of rows and columns, each row and column comprising a number of bits, the device further comprising a controller configured to generate access commands to the memory, an access command identifying an address corresponding to a given row of the memory and a command operation to be performed on said given row, wherein the method comprises:
Dependencies are inferred from the claim text.