Processor that mitigates side channel attacks by preventing all dependent instructions from consuming architectural register result produced by instruction that causes a need for an architectural exception

A method for mitigating side channel attacks, comprising:

• in a microprocessor that comprises a front end that processes instructions in program order and a back end that is configured to perform speculative execution of instructions out of program order in a superscalar fashion, wherein the back end comprises a plurality of execution units comprising one or more producing execution units configured to produce architectural register results during execution of instructions and one or more consuming execution units configured to consume the produced architectural register results during execution of instructions, wherein the producing and consuming execution units may be a same execution unit or different execution units:
• detecting that, during execution by a producing execution unit, an architectural register result producing instruction causes a need for an architectural exception and consequent flush of all instructions younger in program order than the producing instruction;
• and
• preventing all instructions within the back end that are dependent upon the producing instruction from consuming the architectural register result produced by the producing instruction.