Processor that mitigates side channel attacks by expeditiously initiating flushing of instructions dependent upon a load instruction that causes a need for an architectural exception

A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a microprocessor for mitigating side channel attacks (SCA) that attempt to exploit windows of time within which instructions dependent in their execution upon a result of a load instruction may speculatively execute before being flushed by a microprocessor because the load instruction causes a need to raise an architectural exception, wherein the microprocessor comprises a superscalar pipeline having a plurality of execution units configured to execute instructions speculatively and out of program order, the one or more execution units including a load unit configured to execute load instructions, and control logic having at least one input from each of at least two of the execution units for signaling abort requests, wherein the microprocessor is configured by the instructions to perform operations comprising:

• signaling, by the load unit, an abort request to the control logic in response to detecting that a load instruction causes a need for the microprocessor to raise an architectural exception;
• and
• initiating, by the control logic, an abort process as soon as the control logic determines that the abort request from the load unit is highest priority among any other concurrently received abort requests and determines a location of the exception-causing load instruction within the program order of outstanding instructions in the microprocessor;
• and
• wherein performing the abort process comprises flushing from the pipeline all instructions dependent upon a result of the exception-causing load instruction.

A method for mitigating side channel attacks (SCA) that attempt to exploit windows of time within which instructions dependent in their execution upon a result of a load instruction may speculatively execute before being flushed by a microprocessor because the load instruction causes a need to raise an architectural exception, comprising:

• in a microprocessor comprising a superscalar pipeline having a plurality of execution units configured to execute instructions speculatively and out of program order, the one or more execution units including a load unit configured to execute load instructions, and control logic having at least one input from each of at least two of the execution units for signaling abort requests:
• signaling, by the load unit, an abort request to the control logic in response to detecting that a load instruction causes a need for the microprocessor to raise an architectural exception;
• and
• initiating, by the control logic, an abort process as soon as the control logic determines that the abort request from the load unit is highest priority among any other concurrently received abort requests and determines a location of the exception-causing load instruction within the program order of outstanding instructions in the microprocessor;
• and
• wherein performing the abort process comprises flushing from the pipeline all instructions dependent upon a result of the exception-causing load instruction.