US 2022/0067142 A1 · PHYSICALLY-TAGGED DATA CACHE MEMORY THAT USES TRANSLATION CONTEXT TO REDUCE LIKELIHOOD THAT ENTRIES ALLOCATED DURING EXECUTION UNDER ONE TRANSLATION CONTEXT ARE ACCESSIBLE DURING EXECUTION UNDER ANOTHER TRANSLATION CONTEXT

Abstract

A physically-tagged data cache memory mitigates side channel attacks by using a translation context (TC). With each entry allocation, control logic uses the received TC to perform the allocation, and with each access uses the received TC in a hit determination. The TC includes an address space identifier (ASID), virtual machine identifier (VMID), a privilege mode (PM) or translation regime (TR), or combination thereof. The TC is included in a tag of the allocated entry. Alternatively, or additionally, the TC is included in the set index to select a set of entries of the cache memory. Also, the TC may be hashed with address index bits to generate a small tag also included in the allocated entry used to generate an access early miss indication and way select.

Claims21

Dependent claims

A data cache memory for mitigating side channel attacks in a processor that comprises the data cache memory and that includes a translation context (TC), comprising:

a first input that receives a physical memory address;
a second input that receives the TC;
control logic configured to:
with each allocation of an entry of the data cache memory:
use the received physical memory address and the received TC to perform the allocation of the entry;
and
with each access of the data cache memory:
use the received physical memory address and the received TC in a correct determination of whether the access hits in the data cache memory;
and
wherein the TC comprises:
an address space identifier (ASID);
or
a virtual machine identifier (VMID);
or
a privilege mode (PM) or a translation regime (TR);
or
a combination of two or more of the ASID, the VMID, and the PM or the TR.

14 more elements

A method for mitigating side channel attacks in a processor that comprises a data cache memory and that includes a translation context (TC), comprising:

with each allocation of an entry of the data cache memory:
using a received physical memory address and a received TC to perform the allocation of the entry;
and
with each access of the data cache memory:
using the received physical memory address and the received TC in a correct determination of whether the access hits in the data cache memory;
and
wherein the TC comprises:
an address space identifier (ASID);
or
a virtual machine identifier (VMID);
or
a privilege mode (PM) or a translation regime (TR);
or
a combination of two or more of the ASID, the VMID, and the PM or the TR.

11 more elements

Dependencies are inferred from the claim text.

Physically-tagged data cache memory that uses translation context to reduce likelihood that entries allocated during execution under one translation context are accessible during execution under another translation context

Life of this patent

Physically-tagged data cache memory that uses translation context to reduce likelihood that entries allocated during execution under one translation context are accessible during execution under another translation context

Life of this patent

Abstract

Claims21