Bit stream transformation in parallel data interfaces
OwnerAravind GANESAN, Nagalinga Swamy Basayya AREMALLAPUR +2inventors
InventorsAravind GANESAN, Nagalinga Swamy Basayya AREMALLAPUR, Jaiganesh BALAKRISHNAN, Robert Clair KELLER
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Abstract
A circuit includes: a parallel data interface; and transition control circuitry coupled to the parallel data interface. The transition control circuitry is configured to: receive an input bit stream sample; determine a bit transformation pattern for the input bit stream sample in accordance with a target criteria; and generate an output bit stream symbol from the input bit stream sample and the bit transformation pattern, wherein the output bit stream symbol has more bits than the input bit stream sample.
Claims22
A circuit, comprising:
- a parallel data interface;
- and
- transition control circuitry coupled to the parallel data interface, the transition control circuitry is configured to:
- receive an input bit stream sample;
- determine a bit transformation pattern for the input bit stream sample in accordance with a target criteria;
- and
- generate an output bit stream symbol from the input bit stream sample and the bit transformation pattern, wherein the output bit stream symbol has more bits than the input bit stream sample.
A system, comprising:
- a first electronic circuit;
- and
- parallel data interface lanes coupled to the first electronic circuit and adapted to be coupled to a second electronic circuit, wherein the first electronic circuit is configured to:
- receive an input bit stream sample;
- determine a bit transformation pattern for the input bit stream sample in accordance with a target criteria;
- generate an output bit stream symbol from the input bit stream sample and the bit transformation pattern, wherein the output bit stream symbol has more bits than the input bit stream sample;
- and
- provide the output bit stream symbol to the parallel data interface lanes.
A method, comprising:
- receive an input bit stream sample;
- determine a bit transformation pattern for the input bit stream sample in accordance with a target criteria;
- generate an output bit stream symbol from the input bit stream sample and the bit transformation pattern, wherein the output bit stream symbol has more bits than the input bit stream sample;
- and
- provide the output bit stream symbol to parallel data interface lanes.
Dependencies are inferred from the claim text.