Efficient signaling scheme for high-speed ultra short reach interfaces
AssigneeMarvell Asia Pte Ltd
InventorRamin Farjadrad
Life of this patent
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Abstract
A master integrated circuit (IC) chip includes transmit circuitry and receiver circuitry. The transmit circuitry includes a timing signal generation circuit to generate a first timing signal, and a driver to transmit first data in response to the first timing signal. A timing signal path routes the first timing signal in a source synchronous manner with the first data. The receiver circuitry includes a receiver to receive second data from a slave IC chip, and sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.
Claims16
A multi-chip module (MCM), comprising:
- a chip substrate;
- a first integrated circuit (IC) chip disposed on the substrate, the first IC chip including a first data input/output (I/O) port, the first data I/O port including a transmitter circuit to transmit first data and a receiver circuit to receive second data concurrently while transmitting the first data;
- a second integrated circuit (IC) chip disposed on the substrate and packaged with the first IC chip to form an IC chip package, the second IC chip including a second data input/output (I/O) port;
- a first wired channel configured to couple the first data I/O port and the second data I/O port to concurrently and bidirectionally transfer the first data and the second data between the first IC chip and the second IC chip;
- and
- echo interference cancellation circuitry disposed in the first IC chip, the echo interference cancellation circuitry configured to cancel echo interference associated with transmitting the first data over the wired channel while concurrently receiving the second data over the wired channel.
A method of operation in a multi-chip module (MCM), the MCM including a chip substrate, respective first and second integrated circuit (IC) chips disposed on the substrate, and a wired signaling channel coupled between the first and second IC chips, the method comprising:
- transmitting first data from the first IC chip to the second IC chip along the wired signaling channel in a first direction;
- receiving second data with the first IC chip from the second IC chip along the ultra short reach wired signaling channel in a second direction opposite to the first direction, while concurrently transmitting the first data in the first direction, the receiving including canceling echo interference associated with concurrently transmitting the first data.
Dependencies are inferred from the claim text.