Techniques to improve translation lookaside buffer reach by leveraging idle resources

A device, comprising:

• a compute unit;
• and
• a first translation lookaside buffer, wherein the compute unit is configured to:
• detect a first miss for a first address translation request for a first address translation in a first translation lookaside buffer;
• in response to the first miss, fetch the first address translation into the first translation lookaside buffer and evict a second address translation from the translation lookaside buffer into an instruction cache or local data share memory;
• detect a second miss for a second address translation request referencing the second address translation, in the first translation lookaside buffer;
• and
• in response to the second miss, fetch the second address translation from the instruction cache or the local data share memory.

An accelerated processing device (“APD”), comprising:

• a compute unit;
• an instruction cache;
• and
• a local data share memory,
• wherein the compute unit is configured to:
• detect a first miss for a first address translation request for a first address translation in a first translation lookaside buffer;
• in response to the first miss, fetch the first address translation into the first translation lookaside buffer and evict a second address translation from the translation lookaside buffer into the instruction cache or the local data share memory;
• detect a second miss for a second address translation request referencing the second address translation, in the first translation lookaside buffer;
• and
• in response to the second miss, fetch the second address translation from the instruction cache or the local data share memory.