Storage Array Invalidation Maintenance

A non-transitory computer readable medium having stored thereon design information that specifies a circuit design in a format recognized by a fabrication system that is configured to use the design information to fabricate a hardware integrated circuit that comprises:

• a power management circuit configured to:
• determine that a first processor core has transitioned to an idle state in which the first processor core does not execute instructions but is not in a powered-off state;
• receive, while the first processor core is in the idle state, a first set of invalidation requests directed to the first processor core to invalidate a set of entries of a storage array of the first processor core;
• store first invalidation information that is indicative of the first set of invalidation requests;
• determine that the first processor core has received a request to transition from the idle state to a run state in which the first processor core executes instructions;
• and
• prior to the first processor core operating in the run state, invalidate the set of entries of the storage array based on the first invalidation information.

A method, comprising:

• detecting, by a power management circuit of a processing unit, that a processor core of the processing unit has transitioned to an idle state in which the processor core does not execute instructions but is not in a powered-off state;
• while the processor core is operating in the idle state, the power management circuit:
• receiving a first set of invalidation requests directed to the processor core to invalidate a first set of entries of a storage array of the processor core;
• and
• storing first invalidation information that is indicative of the first set of invalidation requests;
• determining, by the power management circuit, that the processor core has received a request to transition to a run state in which the processor core executes instructions;
• and
• prior to the processor core operating in the run state, the power management circuit invalidating the first set of entries of the storage array based on the first invalidation information.