Limited propagation of unnecessary memory updates
AssigneeAdvanced Micro Devices, Inc.
InventorsJohnathan ALSOP, Pouya FOTOUHI, Bradford BECKMANN, Sergey BLAGODUROV
Life of this patent
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Abstract
A processing system limits the propagation of unnecessary memory updates by bypassing writing back dirty cache lines to other levels of a memory hierarchy in response to receiving an indication from software executing at a processor of the processing system that the value of the dirty cache line is dead (i.e., will not be read again or will not be read until after it has been overwritten). In response to receiving an indication from software that data is dead, a cache controller prevents propagation of the dead data to other levels of memory in response to eviction of the dead data or flushing of the cache at which the dead data is stored.
Claims20
A method comprising:
- in response to evicting a dirty cache line from a first cache of a processor, bypassing writing the dirty cache line to a second cache or memory of the processor in response to receiving an indication from software executing at the processor that the dirty cache line is dead.
A method comprising:
- receiving, at a cache controller for a first cache of a processor, the first cache storing a plurality of dirty cache lines, an indication from software executing at the processor that a subset of the dirty cache lines are dead;
- and
- in response to a flush operation or eviction of a dirty cache line from the first cache, selectively writing back only the dirty cache lines not included in the subset of the dirty cache lines to a second cache.
A processor comprising:
- a first cache configured to store dirty cache lines;
- a second cache;
- and
- a cache controller associated with the first cache, the cache controller to:
- receive an indication from software executing at the processor that a dirty cache line is dead;
- and
- in response to a flush operation or eviction of dirty cache lines from the first cache, bypass writing back the dirty cache line to the second cache based on the indication.
Dependencies are inferred from the claim text.