Cache memory having a programmable number of ways

A method of using a cache memory implemented as a single memory block programmable to operate in a direct access mode or an M-ways mode responsive to a way quantity indication, the method comprising:

• with an instruction memory portion of the cache memory, the instruction memory portion comprising a plurality of instruction memory locations, storing instruction data encoding a plurality of CPU instructions;
• with a tag memory portion of the cache memory, the tag memory portion comprising a plurality of tag memory locations, storing tag data encoding address ranges of a RAM memory where the CPU instructions are stored;
• with one or more peripheral circuits of the cache memory, receiving a CPU address corresponding with an address of the RAM memory storing a particular CPU instruction, wherein the CPU address has a plurality of bits divided into a tag portion and an index portion, the tag portion comprising tag data for the for the particular CPU instruction, and the index portion comprising memory address data for the cache memory;
• with the one or more peripheral circuits, receiving the way quantity indication indicating an integer number (M) of ways into which the instruction memory portion and the tag memory portion are to be subdivided, M being 1 for the direct access mode, and M being greater than 1 for the M-ways mode;
• with the one or more peripheral circuits, responsive to M being 1, read the cache memory to retrieve the particular CPU instruction using the index portion as cache memory address data without assessing the tag portion;
• and
• with the one or more peripheral circuits, responsive to M being greater than one, identifying which bits of the CPU address form the tag portion based on the way quantity indication, and determining whether the particular CPU instruction is stored in the cache memory based on the identified tag portion of the CPU address and tag data stored in the cache memory.