Dynamically configurable multi-mode memory allocation in an accelerator multi-core system on chip

At least one computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to:

• determine runtime memory requirements of an artificial intelligence (AI) application;
• define a remote address range for a plurality of memories based on the runtime memory requirements, wherein each memory in the plurality of memories corresponds to a processor in a plurality of processors;
• and
• define a shared address range for the plurality of memories based on the runtime memory requirements, wherein the shared address range is aliased.

A semiconductor apparatus comprising:

• one or more substrates;
• and
• logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to:
• access a remote address range in a linear sequence, wherein the remote address range is associated with a plurality of memories, and wherein each memory in the plurality of memories is to correspond to a processor in a plurality of processors;
• and
• access a shared address range in a hashed sequence, wherein the shared address range is associated with the plurality of memories, and wherein a partition between the remote address range and the shared address range is variable based on runtime memory requirements of an artificial intelligence (AI) application to be executed on one or more of the plurality of processors.