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US 2022/0066920 A1Published application
Memory sub-system codeword addressing
AssigneeMicron Technology, Inc.
InventorReshmi Basu
Life of this patent
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Abstract
A method includes writing a first codeword to a first set of contiguous partitions in a first memory die of a memory device. The method further includes writing a first portion of a second codeword to a second set of contiguous partitions in the first memory die of the memory device and writing a second portion of the second codeword to a first set of contiguous partitions in a second memory die of the memory device. The method also includes writing a third codewords to a second set of contiguous partitions in the second memory die of the memory device.
Claims20
A method, comprising:
- writing a first codeword to a first set of contiguous partitions in a first memory die of a memory device;
- writing a first portion of a second codeword to a second set of contiguous partitions in the first memory die of the memory device, wherein the first portion comprises a first half of the second codeword;
- writing a second portion of the second codeword to a first set of contiguous partitions in a second memory die of the memory device, wherein the second portion comprises a second half of the second codeword;
- and
- writing a third codeword to a second set of contiguous partitions in the second memory die of the memory device.
2 more elements
An apparatus, comprising:
- a memory sub-system codeword addressing component to:
- write a first codeword to a first set of contiguous partitions in a first access row of a memory device;
- write a first half of a second codeword to a second set of contiguous partitions in the first access row of the memory device, wherein the first set of contiguous partitions in the first access row and the second set of contiguous partitions in the access first row are separated by a null partition;
- write a second half of the second codeword to a first set of contiguous partitions in a second access row of the memory device;
- and
- write a third codeword to a second set of contiguous partitions in the second access row of the memory device.
3 more elements
A system, comprising:
- a memory sub-system comprising a plurality of memory devices arranged to form a stackable cross-gridded array of memory cells;
- and
- a processing device coupled to the plurality of memory devices, the processing device to perform operations comprising:
- determining a quantity of addressable partitions in a first hybrid address row of a memory device and a quantity of addressable partitions in a second hybrid address row of the memory device;
- writing a first codeword to the first set of contiguous partitions in the first hybrid access row of the particular memory device;
- writing a first half of a second codeword to a second set of contiguous partitions in the first hybrid access row of the particular memory device;
- writing a second half of the second codeword to a first set of contiguous partitions in the second hybrid access row of the memory device;
- and
- writing a third codeword to a second set of contiguous partitions in the second hybrid access row of the memory device, wherein
- writing to the first set of contiguous portions and the second set of contiguous partitions of the first hybrid access row or the first set of contiguous portions and the second set of contiguous partitions of the second hybrid access row, or both, is based, at least in part, on the determined quantity of addressable partitions in the first hybrid address row of the particular memory device and the quantity of addressable partitions in the second hybrid address row of the particular memory device.
7 more elements
Dependencies are inferred from the claim text.