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US 2022/0066909 A1Published application
Waveform based reconstruction for emulation
AssigneeSynopsys, Inc.
InventorsGagan Vishal Jain, Johnson Adaikalasamy, Alexander John Wakefield, Ritesh Mittal, Solaiman Rahim, Olivier Coudert
Life of this patent
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Abstract
A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.
Claims20
A non-transitory computer readable medium comprising stored instructions, the instructions when executed by a processor cause the processor to:
- receive, from an emulator, waveforms of signals of a plurality of logic circuits, the signals traced by the emulator for a plurality of clock cycles during emulation of the plurality of logic circuits;
- obtain a computerized model of a plurality of logic circuits, the computerized model comprising:
- a first portion of the computerized model corresponding to at least a first logic circuit of the plurality of logic circuits, and
- a second portion of the computerized model corresponding to at least a second logic circuit of the plurality of logic circuits;
- simulate electronically the first logic circuit by a first processing unit using the first portion of the computerized model;
- simulate electronically the second logic circuit by a second processing unit using the second portion of the computerized model;
- and
- generate an output waveform of an output signal of a logic circuit from the plurality of logic circuits for the plurality of clock cycles based on the simulation of the first logic circuit and the second logic circuit.
5 more elements
A system comprising:
- a scheduler processing unit configured to:
- receive, from an emulator, waveforms of signals of a plurality of logic circuits, the signals traced by the emulator for a plurality of clock cycles during emulation of the plurality of logic circuits;
- obtain a computerized model of a plurality of logic circuits, the computerized model comprising:
- a first portion of the computerized model corresponding to at least a first logic circuit of the plurality of logic circuits, and
- a second portion of the computerized model corresponding to at least a second logic circuit of the plurality of logic circuits;
- and
- a plurality of worker processing units configured to:
- simulate electronically the first logic circuit, by a first worker processing unit of the plurality of worker processing units, using the first portion of the computerized model;
- simulate electronically the second logic circuit, by a second worker processing unit of the plurality of worker processing units, using the second portion of the computerized model;
- and
- generate an output waveform of an output signal of a logic circuit from the plurality of logic circuits for the plurality of clock cycles based on the simulation of the first logic circuit and the second logic circuit.
8 more elements
A method comprising:
- receiving, from an emulator, waveforms of signals of a plurality of logic circuits, the signals traced by the emulator for a plurality of clock cycles during emulation of the plurality of logic circuits;
- obtaining a computerized model of a plurality of logic circuits, the computerized model comprising:
- a first portion of the computerized model corresponding to at least a first logic circuit of the plurality of logic circuits, and
- a second portion of the computerized model corresponding to at least a second logic circuit of the plurality of logic circuits;
- simulating electronically the first logic circuit by a first processing unit using the first portion of the computerized model;
- simulating electronically the second logic circuit by a second processing unit using the second portion of the computerized model;
- and
- generating an output waveform of an output signal of a logic circuit from the plurality of logic circuits for the plurality of clock cycles based on the simulation of the first logic circuit and the second logic circuit.
5 more elements
Dependencies are inferred from the claim text.