Integrated circuit and method of operating same

An integrated circuit, comprising:

• an error correction code (ECC) encoder configured to generate a first set of check bits in response to a first set of data;
• a first set of inverters configured to generate a second set of data in response to the first set of data, the second set of data being inverted from the first set of data;
• and
• a first memory cell array comprising:
• a first portion of memory cells coupled to the first set of inverters and configured to store the second set of data;
• and
• a second portion of memory cells coupled to the ECC encoder, and configured to store the first set of check bits.

A method of operating an integrated circuit, the integrated circuit including a first memory cell array, the method comprising:

• generating, by an error correction code (ECC) encoder, a first set of check bits in response to a first set of data;
• generating, by a first set of inverters, a second set of check bits in response to the first set of check bits, the second set of check bits being inverted from the first set of check bits, the first set of inverters being coupled to the ECC encoder;
• storing the first set of data in a first portion of memory cells of the first memory cell array;
• storing the second set of check bits in a second portion of memory cells of the first memory cell array, the second portion of the memory cells being coupled to the first set of inverters;
• receiving, by a second set of inverters, a third set of check bits, and generating a fourth set of check bits in response to the third set of check bits, the fourth set of check bits being inverted from the third set of check bits, and the third set of check bits corresponds to the second set of check bits stored in the second portion of the memory cells, the second set of inverters being coupled to the second portion of the memory cells;
• and
• determining, by a first logic circuit, whether the first memory cell array has been attacked by a user by detecting an invalid codeword, the invalid codeword including the fourth set of check bits and a second set of data, the second set of data corresponds to the first set of data stored in the first portion of the memory cells, and the first logic circuit being coupled to the second set of inverters and the first portion of the memory cells.