US 2022/0066869 A1 · METHOD OF DEMAND SCRUBBING BY PLACING CORRECTED DATA IN MEMORY-SIDE CACHE

Abstract

Systems, apparatuses, and methods related to chiplets are described. A chiplet-based system may include a memory controller chiplet to control accesses to a storage array, and the memory controller chiplet can facilitate error correction and cache management in a manner to minimize interruptions to a sequence of data reads to write corrected data from a prior read back into the storage array. For example, a read command may be received at a memory controller device of the memory system from a requesting device. Data responsive to the read command may be obtained and determined to include a correctable error. The data may be corrected, transmitted to the requesting device and written to cache of the memory controller device with an indication that data is valid and dirty (e.g., includes an error or corrected error). The data is written back to the memory array in response to a cache eviction event.

Claims20

Dependent claims

A memory system comprising:

a memory array including memory cells;
and
a memory controller operatively coupled to the memory array and including a memory controller cache, wherein the memory controller includes processing circuitry, and is configured to:
decode a memory read request from the host device;
obtain read data for the memory read request from a memory array of the memory device according to a memory address;
detect that the read data has a correctable error;
return corrected read data to the host device in response to the memory request;
store the corrected read data in the memory controller cache and indicate a state of the corrected read data as valid and dirty in response to detecting that the read data has the correctable error;
and
determine a cache eviction event and write corrected read data to the memory array in response to the cache eviction event.

7 more elements

A method of operating a memory system, the method comprising:

receiving a read command at a memory controller device of the memory system from a second device;
obtaining data responsive to the read command from a memory array of the memory system according to a memory address and associated with the read command;
detecting that the data has a correctable error;
transmitting corrected data to the second device in response to the read command;
writing the corrected data in a cache of the memory controller device and indicating a state of the corrected data as valid and dirty in response to detecting that the data has the correctable error;
and
writing the corrected data from the cache to the memory array in response to a cache eviction event.

4 more elements

A non-transitory computer readable storage medium comprising instructions configured to cause a memory controller of a memory system to:

decode a memory read request from a requesting device;
obtain read data for the memory read request from a memory array of the memory system according to a memory address;
detect that the read data has a correctable error:
return corrected read data to the requesting device in response to the memory request;
store the corrected read data in a memory controller cache of the memory system and indicate a state of the corrected read data as valid and dirty in response to detecting that the read data has the correctable error;
and
determine a cache eviction event and write corrected read data to the memory array in response to the cache eviction event.

4 more elements

Dependencies are inferred from the claim text.

Method of demand scrubbing by placing corrected data in memory-side cache

Life of this patent

Method of demand scrubbing by placing corrected data in memory-side cache

Life of this patent

Abstract

Claims20