Memory device with configurable error correction modes

An apparatus, comprising:

• a memory device configured for operating using a first codeword size configuration or a second codeword size configuration, wherein the first codeword size configuration is associated with a first quantity of data bits and a first quantity of error correction code (ECC) bits, and wherein the second codeword size configuration is associated with a second quantity of data bits and a second quantity of ECC bits, and wherein the memory device is configured to:
• operate, when configured with the first codeword size configuration, in a first mode for concurrently performing a plurality of single error correction (SEC) operations on a plurality of codewords with the first quantity of ECC bits;
• and
• operate, when configured with the second codeword size configuration, in a second mode for performing a single error correction double error detection (SECDED) operation on a single codeword with the second quantity of ECC bits.

An apparatus, comprising:

• a memory device configured for operating using a first configuration associated with a first codeword size or a second configuration associated with a second codeword size greater than the first codeword size, wherein the memory device is configured to:
• operate, when configured with the first configuration, in a first mode for concurrently performing a plurality of single error correction (SEC) operations, wherein performing the plurality of SEC operations comprises:
• receiving first data and second data from a host device for a write operation to store data in an array of memory cells of the memory device;
• identifying a first error correction code (ECC) codeword for the first data and a second ECC codeword for the second data, the first ECC codeword and the second ECC codeword associated with the first codeword size;
• storing the first data, the first ECC codeword, the second data, and the second ECC codeword in the array of memory cells;
• retrieving the first and second ECC codewords for a first read operation to read the first data and the second data from the array of memory cells;
• generating a third ECC codeword and a fourth ECC codeword based at least in part on the retrieving;
• and
• detecting a first error based at least in part on comparing the first ECC codeword and the third ECC codeword or on comparing the second ECC codeword and the fourth ECC codeword;
• and
• operate, when configured with the second configuration, in a second mode for performing a single error correction double error detection (SECDED) operation.

A method, comprising:

• identifying that a memory device that supports operating in a first mode for performing at least one single error correction (SEC) operation and a second mode for performing a single error correction double error detection (SECDED) operation is operating in the second mode;
• identifying that the memory device configured for operating using a first configuration associated with a first codeword size and a second configuration associated with a second codeword size is operating using the second configuration, wherein the first configuration is associated with at least a first quantity of data bits and a first quantity of error correction code (ECC) bits, and wherein the second configuration is associated with at least a second quantity of data bits and a second quantity of ECC bits;
• receiving, by the memory device operating in the second mode and using the second configuration associated with the second codeword size, the second quantity of data bits over a channel;
• determining, by the memory device based at least in part on receiving the first quantity of data bits over the channel, the second quantity of ECC bits associated with the second quantity of data bits using the SECDED operation;
• storing the second quantity of data bits and the second quantity of ECC bits in an array of memory cells;
• retrieving the second quantity of data bits and the second quantity of ECC bits from the array of memory cells;
• and
• performing the SECDED operation on the second quantity of data bits retrieved from the array of memory cells using the second quantity of ECC bits retrieved from the array of memory cells based at least in part on the memory device operating in the second mode and operating using the second configuration associated with the second codeword size.