Centralized access control circuit for controlling access to peripherals

A system-on-chip (SoC), comprising:

• a set of processor cores including a first processor core;
• at least one peripheral comprising at least one peripheral register, wherein the peripheral register includes a plurality of bytes;
• and
• a centralized access control circuit that is coupled to the set of processor cores and the peripheral to control access privileges of the set of processor cores for accessing the peripheral, the centralized access control circuit comprising:
• a memory that includes a plurality of lock bits mapped to the plurality of bytes, respectively;
• a first sub-circuit that is configured to:
• receive, from the first processor core, a first access request to access a set of bytes of the plurality of bytes, wherein the first access request includes a first identifier of the first processor core and a first address of the set of bytes;
• and
• grant, based on the first identifier and the first address, a first level of access privilege to the first processor core, for accessing the peripheral;
• and
• a memory controller that is coupled to the memory and the first sub-circuit, and configured to:
• receive the first access request;
• and
• grant, based on a value of each of a set of lock bits mapped to the set of bytes, a second level of access privilege to the first processor core for accessing the set of bytes, wherein the plurality of lock bits include the set of lock bits, and wherein the set of bytes is accessed by the first processor core based on the first and second levels of access privileges.

A method for controlling access privileges of a processor core for accessing at least one peripheral, wherein the peripheral includes at least one peripheral register having a plurality of bytes, the method comprising:

• storing, by a centralized access control circuit, a plurality of lock bits mapped to the plurality of bytes, respectively;
• receiving, by the centralized access control circuit from the processor core, an access request to access a set of bytes of the plurality of bytes, wherein the access request includes an identifier of the processor core and an address of the set of bytes;
• granting, by the centralized access control circuit, based on the identifier and the address, a first level of access privilege to the processor core for accessing the peripheral;
• and
• granting, by the centralized access control circuit, based on a set of lock bits mapped to the set of bytes, a second level of access privilege to the processor core for accessing the set of bytes, wherein the plurality of lock bits include the set of lock bits, and wherein the set of bytes is accessed by the processor core based on the first and second levels of access privileges.