System and method for modeling memory devices with latency

Abstract

Systems and methods for emulate or prototyping of hardware, such as memory, are disclosed. A memory compiler may receive information, such as system calls, indicative of one or more aspects of latency. Responsive to the information, the memory compiler may create infrastructure, such as pipelines and FIFOs, based on the aspects of latency, for emulation or prototyping of the hardware. Using the created infrastructure may improve emulation compile speed, such as by creating a pipeline-based cache structure, and may improve emulation runtime speed, such as by utilizing earlier unused model clocks to fetch data from host sooner.

Dependencies are inferred from the claim text.