Systems and methods for extending a live range of a virtual scalar register
AssigneeHuawei Technologies Co., Ltd.
InventorsAbraham Davidson Fai Chung CHAN, Tyler Bryce NOWICKI, Guansong ZHANG, Ahmed Mohammed ElShafiey Mohammed ELTANTAWY
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Abstract
Systems and methods are described for extending a live range for a virtual scalar register during compiling of a program, comprising: receiving an intermediate representation (IR) of a source code configured for implementing single-instruction-multiple-thread (SIMT) execution, the IR representing the source code as control flow graph including a plurality of basic blocks (BB); and when a virtual scalar register defined in a first BB of the IR is last used in a second BB of the IR that is a divergent BB, modifying the IR to extend the live range of the virtual scalar register.
Claims20
A computer-implemented method performed during compiling of a program, comprising:
- receiving an intermediate representation (IR) of a source code configured for implementing single-instruction-multiple-thread (SIMT) execution, the IR representing the source code as a control flow graph including a plurality of basic blocks (BB);
- and
- when a virtual scalar register defined in a first BB of the IR is last used in a second BB of the IR that is a divergent BB, modifying the IR to extend the live range of the virtual scalar register.
A system comprising:
- a processing device;
- a non-transitory storage storing instructions that configure the processing device to:
- receive an intermediate representation (IR) of a source code configured for implementing single-instruction-multiple-thread (SIMT) execution, the IR representing the source code as control flow graph including a plurality of basic blocks (BB);
- and
- when a virtual scalar register defined in a first BB of the IR is last used in a second BB of the IR that is a divergent BB, modify the IR to extend the live range of the virtual scalar register.
A computer-readable storage medium storing machine-executable instructions that when executed by a processing device cause the processing device to:
- receive an intermediate representation (IR) of a source code configured for implementing single-instruction-multiple-thread (SIMT) execution, the IR representing the source code as control flow graph including a plurality of basic blocks (BB);
- and
- when a virtual scalar register defined in a first BB of the IR is last used in a second BB of the IR that is a divergent BB, modify the IR to extend the live range of the virtual scalar register.
Dependencies are inferred from the claim text.