Accelerating processor based artificial neural network computation
AssigneeInfineon Technologies AG
InventorsAndrew Stevens, Wolfgang Ecker, Sebastian Prebeck
Life of this patent
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Abstract
An apparatus employed in a processing device comprises a processor configured to process data of a predefined data structure. A memory fetch device is coupled to the processor and is configured to determine addresses of the packed data for the processor. The packed data is stored on a memory device that is coupled to the processor. The memory fetch device is further configured to provide output data based on the addresses of the packed data to the processor, where the output data is configured according to the predefine data structure.
Claims20
An apparatus employed in a processing device comprising:
- a processor configured to process data of a predefined data structure;
- a memory fetch device, coupled to the processor, configured to:
- determine addresses of packed data for the processor, wherein the packed data is stored on a memory device that is coupled to the processor;
- and
- provide output data based on the addresses of the packed data to the processor, wherein the output data is configured according to the predefined data structure.
An apparatus for an artificial neural network (ANN) comprising:
- a microcontroller, configured to be coupled to a memory device and configured to process a data stream, wherein the data stream is configured to match at least one of a predefined precision, predefined layout or predefined data structure;
- a data streaming fetch device, coupled to the memory device and the microcontroller, configured to process data stored on the memory device and provide a continuous output stream to the microcontroller, wherein the data streaming fetch device comprises:
- an address generator component configured to generate a plurality of data addresses of the data stored on the memory device;
- a data fetch component configured to import selected data from the memory device based on the plurality of data addresses;
- and
- a data formatting component configured to provide the continuous output stream to the microcontroller.
A method for an artificial neural network (ANN), comprising:
- determining, via a memory fetch device, a plurality of addresses of packed data stored on a memory device and a suppression indicator, wherein the suppression indicator identifies a subset of the plurality of addresses that are associated with generated packed data on the memory device;
- fetching, via the memory fetch device, stored packed data from the memory based on the plurality of addresses and the suppression indicator;
- generating, via the memory fetch device, generated packed data based on the suppression indicator;
- and
- constructing, via the memory fetch device, formatted data from the stored packed data or the generated packed data based on a predefined data structure of a microcontroller.
Dependencies are inferred from the claim text.