Analog Dot Product Multiplier
AssigneeRedpine Signals, Inc.
InventorsAravinth Kumar AYYAPPANNAIR RADHADEVI, Sesha Sairam REGULAGADDA
Life of this patent
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Abstract
A dot product multiplier for matrix operations for an A matrix of order 1×m with a coefficient B matrix of order m×m. Processing Elements (PEs) are arranged in an m×m array, the columns of the array summed to provide a dot product result. Each of the PEs contains a sign determiner and a plurality of analog multiplier cells, one multiplier cell for each value bit. The multipliers operate over four clock cycles, initializing a capacitor charge according to sign on a first clock phase, sharing charge on a second phase, canceling charge on a third phase, and outputting the resultant charge on a fourth phase, the resultant charge on each column representing the dot product for that column.
Claims17
1) A dot product multiplier for multiplying a 1×m A matrix with an m×m B matrix to form a dot product, each element of the A matrix and each element of the B matrix comprising a sign bit and value bits, the dot product multiplier comprising:
- a clock generator providing four non-overlapping phases of clock per clock cycle, the four phases being PH1, PH2, PH3, PH4;
- a plurality of processing elements arranged in said m columns and said m rows, each processing element receiving an ‘a’ element of the A matrix and a ‘b’ element of the B matrix and generating a processing element output;
- each processing element comprising:
- a sign voltage source providing a sign voltage which is a positive voltage for positive multiplication results and a comparatively negative voltage for negative multiplication results based on a sign bit of the ‘a’ element and sign bit of the ‘b’ element;
- a bit multiplier for each particular ‘a’ element value bit an and each ‘b’ element value bit bn, each bit multiplier having an output, the bit multiplier comprising:
- a capacitor having a capacitance Cref*2n, the capacitor initialized to the sign voltage during a first clock phase PH1 if an=1, and initialized to 0V if an=0;
- the bit multiplier coupling the capacitor to capacitors of other bit multipliers during the second clock phage PH2;
- the bit multiplier zeroing the charge on the capacitor if bn=0 on a third clock phase PH3;
- the bit multiplier coupling the capacitor of the bit multiplier to the processing element output during the fourth phase PH4
- each of the m columns having an accumulator, the accumulator receiving a transferred charge from the bit multiplier outputs in a respective column during the fourth phase PH4;
- each accumulator converting the transferred charge to a digital value indicating a dot product value for an associated column.
9) A process for forming dot products of a 1×m A matrix with an m×m B matrix, the process operative on an m column and m row array of processing elements, the A matrix and the B matrix having elements comprising a sign bit and n value bits, each processing element comprising a sign voltage source and a plurality n of multipliers, each multiplier operative on a unique bit n of a value of the A matrix and a value of the B matrix, the process comprising:
- charging a capacitor in each multiplier to a sign voltage provided by the sign voltage source during a first clock phase PH1 if a corresponding bit an is 1;
- sharing capacitor charge across all multiplier capacitors during a second clock phase PH2;
- clearing a charge from the multiplier capacitor if bn is 0 during third clock phase PH3;
- connecting all processing element multiplier capacitors of each column together and converting the charge of each column to a digital output value during a fourth clock phase PH4.
16) A Processing Element (PE) cell for forming an analog product of an ‘a’ value and a ‘b’ value, the ‘a’ value and ‘b’ value having a sign bit and a plurality n of value bits, the PE cell comprising:
- a sign voltage generator comparing the sign bit of the ‘a’ value and the ‘b’ value and generating an output voltage VrefP if the ‘a’ sign bit and ‘b’ sign bit are the same and generating an output value VrefN if the ‘a’ sign bit and ‘b’ sign bit are different values;
- a plurality of multipliers, each multiplier comprising:
- a capacitor having a first terminal coupled to an output switch;
- the capacitor having a second terminal coupled to the first terminal during a first clock phase if an=0 and coupled to the sign determiner output if an=1 during the first clock phase PH1;
- the capacitor having a ClkCHSH1 switch coupling the second terminal of the capacitor to VCM during the first clock phase PH1 when an=1;
- the capacitor first terminal connected to a multiplier output, the multiplier output connected to other multiplier outputs during a second clock phase PH2;
- the capacitor first terminal and capacitor second terminal both coupled to VCM during a third clock phase PH3 if bn=0;
- the capacitor second terminal coupled to VCM during a fourth clock phase PH4;
- during a fourth phase PH4, the processing element operative to couple the capacitor first terminal of all multipliers to a processing element output, the processing element also coupling the capacitor second terminal to VCM, the processing element output thereby generating an analog capacitor charge value proportional to the multiplication of A*B.
17) An analog multiplier having a first digital input and a second digital input and forming an analog output coupled to a successive approximation (SA) analog to digital converter (ADC) having a plurality of switched capacitors, the analog multiplier comprising:
- a multiplier cell for multiplying the first digital input with the second digital input and forming an analog output;
- a magnitude estimator forming a sum equal to the number of most significant bits of the first digital input and second digital input which are zero;
- the SA ADC performing a successive approximation where the plurality of switched capacitors are initially configured based on the magnitude estimator sum.
Dependencies are inferred from the claim text.