Memory system and controlling method of memory system
AssigneeKioxia Corporation
InventorsChihoko SHIGETA, Kazuya KITSUNAI
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Abstract
According to one embodiment, a memory system includes a first and second nonvolatile memory each including a plurality of memory cells; and a memory controller configured to perform, in parallel, a first set of write processes sequentially performed on the first nonvolatile memory, and a second set of write processes sequentially performed on the second nonvolatile memory. The memory controller is configured to change a setting of at least one unperformed write process among the first set and second set of write processes based on differences in progress between the first set and second set of write processes, the first set and second set of write processes being performed in parallel.
Claims20
A memory system comprising:
- a first nonvolatile memory and a second nonvolatile memory each including a plurality of memory cells;
- and
- a memory controller configured to perform, in parallel, a first set of write processes sequentially performed on the first nonvolatile memory, and a second set of write processes sequentially performed on the second nonvolatile memory,
- wherein the memory controller is configured to change a setting of at least one unperformed write process among the first set of write processes and the second set of write processes based on differences in progress between the first set of write processes and the second set of write processes, the first set of write processes and the second set of write processes being performed in parallel.
A controlling method of a memory system, the memory system comprising a first nonvolatile memory and a second nonvolatile memory each including a plurality of memory cells, the method comprising:
- performing, in parallel, a first set of write processes sequentially performed on the first nonvolatile memory, and a second set of write processes sequentially performed on the second nonvolatile memory;
- changing a setting of at least one unperformed write process among the first set of write processes and the second set of write processes based on differences in progress between the first set of write processes and the second set of write processes, the first set of write processes and the second set of write processes being performed in parallel.
Dependencies are inferred from the claim text.