Memory device
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Tsing Hua University
InventorsJun-Shen WU, Chi-En WANG, Ren-Shuo LIU
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Abstract
A memory device is disclosed, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.
Claims20
A memory device, comprising:
- a memory array, wherein at least one first faulty cell and at least one second faulty cell that are in the memory array are configured to store data corresponding to, respectively, first and second fields of a floating-point number;
- and
- a selection circuit configured to identify the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell,
- wherein the selection circuit is further configured to output a fault address of the at least one first faulty cell to a redundancy analyzer circuit that is configured to perform a replacing operation of replacing the at least one first faulty cell.
A method, comprising:
- testing a memory array to identify a plurality of faulty cells in the memory array;
- identifying in the plurality of faulty cells an excluded cell that meets at least one condition, wherein the at least one condition is associated with a value of a first binary number corresponding to the excluded cell;
- and
- replacing at least one cell of remaining cells in the plurality of faulty cells with a redundant cell.
A system, comprising:
- a memory device;
- and
- a neural network processor configured to access the memory device;
- wherein the memory device comprises:
- a plurality of memory cells configured to store a plurality of binary numbers corresponding to data transmitted from/to the neural network processor;
- a selection circuit configured to output a fault address of a faulty cell in the plurality of memory cells, wherein the faulty cell has a first priority in a cell replacement operation and has a stuck-at-1 fault in a bit in an exponent field of a binary number of the plurality of binary numbers;
- and
- a replacement circuit configured to replace, according to the fault address, the faulty cell with a redundant cell of a plurality of redundant cells.
Dependencies are inferred from the claim text.