Data dispersion-based memory management
AssigneeMicron Technology, Inc.
InventorsAshutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
Life of this patent
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Abstract
A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.
Claims20
A method, comprising:
- determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells;
- based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells;
- based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells;
- and
- performing a folding operation on the selected block of NAND memory cells.
An apparatus, comprising:
- a data dispersion-based memory management component configured to:
- determine a respective number of and respective locations of valid translation units in a plurality of interleaved NAND memory blocks of a memory component;
- based on the respective number of the valid translation units, determine respective valid translation unit counts of the plurality of interleaved NAND memory blocks;
- based on the respective locations of the valid translation units, determine respective dispersions of the valid translation units in the plurality of interleaved NAND memory blocks;
- based on a respective valid translation unit count and a respective dispersion of the valid translation units of the memory block, select an interleaved NAND memory block from the plurality of interleaved NAND memory blocks;
- and
- perform a folding operation on a portion of the selected interleaved NAND memory block.
A system, comprising:
- a memory sub-system comprising a plurality of memory components arranged to form a stackable cross-gridded array of a plurality of superblocks of interleaved NAND memory cells;
- and
- a processing device coupled to the plurality of memory components, the processing device to perform operations comprising:
- determining a respective valid translation unit count (VTC) of each superblock of the plurality of superblocks;
- determining the respective VTC of a subset of the plurality of superblocks is less than a validity threshold;
- based on determining that the respective VTC of the subset of the plurality of superblocks is less than the validity threshold, designating the subset as candidate superblocks;
- determining respective dispersions of valid translation units in each of the candidate superblocks;
- selecting a candidate superblock based on the respective dispersions of the translation units;
- and
- performing a folding operation on the selected superblock.
Dependencies are inferred from the claim text.