Memory system including a nonvolatile memory and control method
AssigneeKioxia Corporation
InventorMasahiro TAKESHITA
Life of this patent
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Abstract
According to one embodiment, a memory system includes a memory system includes a first nonvolatile memory and a controller. The controller controls the first nonvolatile memory. The second memory system includes a second nonvolatile memory. The controller manages information indicative of correspondences between private logical addresses and public logical addresses. The private logical addresses include first private logical addresses and second private logical addresses. Each of the first private logical addresses specifies a location in a first logical address space corresponding to the first nonvolatile memory. Each of the second private logical addresses specifies a location in a second logical address space corresponding to the second nonvolatile memory.
Claims20
A memory system comprising:
- a first nonvolatile memory;
- and
- a controller configured to control the first nonvolatile memory and is capable of communicating with a host and a second memory system via a network, wherein
- the second memory system includes a second nonvolatile memory, wherein
- the controller is configured to:
- manage information indicative of correspondences between private logical addresses and public logical addresses, the private logical addresses including first private logical addresses and second private logical addresses, each of the first private logical addresses specifying a location in a first logical address space corresponding to the first nonvolatile memory, each of the second private logical addresses specifying a location in a second logical address space corresponding to the second nonvolatile memory, each of the public logical addresses specifying a location in a third logical address space over the first nonvolatile memory and the second nonvolatile memory;
- receive a first write request designating a first public logical address or a first read request designating the first public logical address from the host;
- specify a third private logical address corresponding to the first public logical address;
- perform, responsive to determining the third private logical address is included in the first private logical addresses, a write process with respect to the third private logical address or a read process with respect to the third private logical address;
- and
- transmit, responsive to determining the third private logical address is included in the second private logical addresses, a second write request designating the third private logical address or a second read request designating the third private logical address to the second memory system.
A control method of a memory system that is capable of connecting with a host and a second memory system via a network, the memory system including a first nonvolatile memory and the second memory system including a second nonvolatile memory, the method comprising:
- managing information indicative of correspondences between private logical addresses and public logical addresses, the private logical addresses including first private logical addresses and second private logical addresses, each of the first private logical addresses specifying a location in a first logical address space corresponding to the first nonvolatile memory, each of the second private logical addresses specifying a location in a second logical address space corresponding to the second nonvolatile memory, each of the public logical addresses specifying a location in a third logical address space over the first nonvolatile memory and the second nonvolatile memory;
- receiving a first write request designating a first public logical address or a first read request designating the first public logical address from the host;
- specifying a third private logical address corresponding to the first public logical address;
- performing, responsive to determining the third private logical address is included in the first private logical addresses, a write process with respect to the third private logical address or a read process with respect to the third private logical address;
- and
- transmitting, responsive to determining the third private logical address is included in the second private logical addresses, a second write request designating the third private logical address or a second read request designating the third private logical address to the second memory system.
An information processing system including a host, a first memory system, and a second memory system that are mutually connectable via a network,
- the first memory system comprising a first nonvolatile memory, and
- the second memory system comprising a second nonvolatile memory, wherein
- the first memory system is configured to:
- manage information indicative of correspondences between private logical addresses and public logical addresses, the private logical addresses including first private logical addresses and second private logical addresses, the first private logical addresses specifying a location in a first logical address space corresponding to the first nonvolatile memory, the second private logical addresses specifying a location in a second logical address space corresponding to the second nonvolatile memory, the public logical addresses specifying a location in a third logical address space over the first nonvolatile memory and the second nonvolatile memory;
- receive a first write request designating a first public logical address or a first read request designating the first public logical address from the host;
- specify a third private logical address corresponding to the first public logical address;
- perform, responsive to determining the third private logical address is included in the first private logical addresses, a write process with respect to the third private logical address or a read process with respect to the third private logical address;
- and
- transmit, responsive to determining the third private logical address is included in the second private logical addresses, a second write request designating the third private logical address or a second read request designating the third private logical address to the second memory system.
Dependencies are inferred from the claim text.