Memory system and controlling method
AssigneeKioxia Corporation
InventorDaisuke TAKI
Life of this patent
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Abstract
According to one embodiment, a memory system is connectable to a host as a type 3 compute express link (CXL) device. A controller of the memory system packs, at a CXL link layer, a response command with data (DRS) and/or a response command without data (NDR), received from an upper CXL transaction layer, into a flit including four slots, and transmits the response command to a lower CXL ARB/MUX layer, and selects, based on a remaining number of data slots of DRS packed in a first flit that has been transmitted to the CXL ARB/MUX layer, a remaining number of DRS, a remaining number of NDR, and a number of empty slots in a second flit to be transmitted subsequently to the CXL ARB/MUX layer, a format to be used in slots in a second flit.
Claims12
A memory system connectable to a host as a type 3 compute express link (CXL) device via an interface conforming to a CXL standard, the memory system comprising:
- a nonvolatile memory;
- and
- a controller configured to control writing of data to the nonvolatile memory or reading of data from the nonvolatile memory in response to a command from the host,
- wherein the controller is configured to:
- pack, at a CXL link layer, a response command with data (DRS:
- data response) and/or a response command without data (NDR:
- no data response), received from an upper CXL transaction layer, into a flit including four slots, and transmit the response command to a lower CXL ARB/MUX layer;
- and
- select, based on a remaining number of data slots of DRS packed in a first flit that has been transmitted to the CXL ARB/MUX layer, a remaining number of DRS, a remaining number of NDR, and a number of empty slots in a second flit to be transmitted subsequently to the CXL ARB/MUX layer, a format to be used in slots in the second flit.
A controlling method of a type 3 compute express link (CXL) device including an interface conforming to a CXL standard, the method comprising
- packing, at a CXL link layer of the type 3 CXL device, a response command with data (DRS:
- data response) and/or a response command without data (NDR:
- no data response), received from an upper CXL transaction layer, into a flit including four slots, and transmitting the response commands to a lower CXL ARB/MUX layer,
- wherein the packing includes selecting, based on a remaining number of data slots of DRS packed in a first flit that has been transmitted to the CXL ARB/MUX layer, a remaining number of DRS, a remaining number of NDR, and a number of empty slots in a second flit to be transmitted subsequently to the CXL ARB/MUX layer, a format to be used in slots in the second flit.
Dependencies are inferred from the claim text.