Mass fabrication-compatible processing of semiconductor metasurfaces

A method comprising:

• providing a layer structure, with the layer structure including a substrate, a layer stack, and resist structures made of a resist material, with the resist material including a semiconductor element, wherein the layer stack is arranged on top of the substrate, the resist structures form a pattern on the layer stack, and the layer stack includes a semiconductor layer on top of the substrate;
• providing a protective layer on top of the semiconductor layer with a transfer layer on top of the protective layer;
• removing exposed portions of the transfer layer that are not masked by the resist structures by selectively etching the transfer layer, whereby residual portions of the transfer layer remain between the protective layer and the resist structures;
• removing the resist structures by selectively etching the transfer layer, to expose transfer layer structures formed by said residual portions of the transfer layer;
• transferring the transfer layer structures into the protective layer by selectively etching the protective layer, to obtain combined portions that comprise residual portions of the protective layer and residual portions of the transfer layer;
• selectively etching the semiconductor layer to obtain residual semiconductor structures, which are masked by the combined portions, with the selectively etched semiconductor layer being selectively patterned using a BCl3-based inductively coupled plasma (ICP) process;
• and
• removing the combined portions by selectively etching the residual semiconductor structures to expose the semiconductor structures and thereby obtain metasurface structures that are arranged according to the pattern on the layer stack.